Many organizations or companies use server computers to provide services such as cloud computing, analytics, web services, storage, databases, applications, deployment services, etc. to a potentially larger number of client computers. The clients can use these services to power a wide variety of workloads such as storage, data processing and warehousing, executing of web and mobile applications, archiving and many other tasks. The demand for higher processing power as well as memory capacity and performance is constantly rising for both the client computers and the server computers.
Server computers generally utilize multiple sockets to house multiple system on chips (SoCs) to support higher processing power. Each SoC may include multiple processors and integrated memory controllers to access memory coupled to the SoC. In many instances, multi-socket server computers are based on respective non-uniform memory access (NUMA) architecture and face several limitations. For example, in a server computer based on NUMA architecture, memory latency may vary for different SoCs based on whether the memory is local, or one or more hops away from an SoC trying to access the memory. Thus, in most instances, the multi-socket server computers based on the NUMA architecture may not be able to provide uniform access to the memory to each of the processors on each of the SoCs. Also, if an SoC fails or switches to low power mode, the memory associated with that SoC may not be available to other socket processors.
Additionally, as the number of memory controllers are increased in each of the SoCs to keep up with the increasing demand for higher memory capacity in the multi-socket server computers, the number of pins on the SoC package and the physical routing of the memory channels on a printed circuit board (PCB) to support the higher number of memory controllers can be a challenge. In most instances, the multi-socket server computers may not be able to support the higher memory capacity without increasing the number of pins on the SoC package or adding complexity in the PCB layout.